The present invention relates to a high speed microprocessor zero detection circuit with 32-bit and 64-bit modes.
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. Utilizing SOI technology designers can increase the speed of digital logic integrated circuits while reducing their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
As shown in FIG. 1, SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon dioxide (SiO2) or glass, and a MOS transistor built on top of this structure. The main advantage of constructing the MOS transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal capacitance of the transistor increases its operating speed. With SOI technology faster MOS transistors can be manufactured resulting in higher performance semiconductors for faster electronic devices.
Referring to FIGS. 1 and 2, there is shown the SOI FET and the parasitic bipolar device. With SOI FETs, by placing a MOS transistor on top of a SOI layer, the MOS transistor is actually placed in parallel with a bipolar junction transistor, as illustrated in FIG. 2. If enough current is passed through the MOS transistor, the parasitic bipolar transistor will turn on. The parasitic bipolar transistor has a small current gain.
Normally, parasitic bipolar action does not manifest itself in conventional, bulk, NMOS transistors because the base of the bipolar transistor is always kept at ground potential, keeping the bipolar transistor turned off. In conventional, bulk, PMOS transistors the body of the PFET is tied to a supply rail Vdd. In the SOI FET, the body (B) of the MOS FET device, or base of the bipolar transistor, is floating and can be charged high by junction leakages induced when both drain (D) and source (S) terminals of the MOS FET are at a high potential. Subsequently, if the source (S) is pulled to a low potential, the trapped charge in the base area (B) is available as parasitic base current. The parasitic base current activates the bipolar transistor and generates a collector current at the drain terminal of the MOS FET.
In Arithmetic Logic Units (ALUs) it is necessary to set a condition code register after an arithmetic operation to specify whether or not the result of the operation was zero. The circuits that accomplish this are typically critical timing paths of the microprocessor. A complication is that the ALU must support not only 64-bit data, but also 32-bit data in order to maintain backward compatibility with previous generations of microprocessors.
FIG. 3 shows a typical Domino circuit that would be used as part of a large circuit implementing this function. If zero detection on only 32 bits of the 64-bit datum is desired, the MODE64 signal will be set to 0 on some instances of this circuit, thus disabling the other 32-bits that are not to be included in the computation. This feature is also very important in improving the testability of the Zero-Detection circuit. It is very difficult to make this circuit work with Silicon-on-Insulator (SOI) technology because the bipolar discharge problem associated with SOI technology is very severe for this particular topology.
The 32/64-bit selection has to be included in the NFET tree via transistors T0 to TN, which introduces the bipolar discharge problem because the bodies of transistors N0 through NN can now be charged to the power supply. The number of NMOS transistor stacks, N in FIG. 3, must be large because when the entire circuit is put together it must cover all 64 bits of the datum. N will be anywhere from 4 to 16, which makes the bipolar discharge problem severe, and because the transistors in the stack must be very large to meet the timing requirements, the problem is even more severe. The resulting error from the bipolar discharge is that node PRE may be accidentally discharged, thus giving an incorrect result in the machine.
A principal object of the present invention is to provide a zero-detection circuit. Other objects are to provide such a zero-detection circuit substantially without negative effects and that overcomes many of the disadvantages of prior art arrangements.
In brief, a zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the plurality of input transistors receives a data input. An intermediate node is connected to the input transistor stacks. An output stage is coupled to the intermediate node providing an output. The output stage includes a bit selection control circuit receiving a bit selection signal. The bit selection control circuit provides a zero level output of the output stage responsive to a predefined bit selection signal.
In accordance with features of the invention, the transistor stacks comprise silicon-on-insulator (SOI) transistors.